LTC1099ACN#PBF【PDF 14/16 页】IC A/D CONV 8BIT HI-SPEED 20-DIP

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LTC1099

FUNCTIONAL DESCRIPTIO

Figure 5 shows the functional block diagram for the

LTC1099 2-step flash ADC. It consists of two 4-bit flash

converters, a 4-bit DAC and a differencing circuit. The

conversion process proceeds as follows:

1. At the start of the conversion, the on-board sample-

and-hold switches from the sample to the hold mode.

This is a true sample-and-hold with an acquisition time

of 240ns, an aperture time of 110ns and a tracking rate

of 2.5V/

2. The held input voltage is converted by the 4-bit MS-

Flash ADC. This generates the upper or most significant

4-bits of the 8-bit output.

3. A 4-bit approximation, from the DAC output, is sub-

tracted from the held input voltage.

4. The LS-Flash ADC converts the difference between the

held input voltage and the DAC approximation. This

generates the lower or least significant (LS) 4-bits of

the 8-bit output. The LS-Flash reference is one six-

teenth of the MS-Flash reference. This effectively mul-

tiplies the difference by 16.

5. Upon the completion of the LS 4-bit flash the eight

output latches are updated simultaneously. At the same

time, the sample-and-hold is switched from the hold

mode to the acquire mode in preparation for the next

conversion.

The advantage of this approach is the reduction in the

amount of hardware required. A full flash converter re-

quires 255 comparators while this approach requires only

31. The price paid for this reduction in hardware is an

increase in conversion time. A full flash converter requires

only one comparison cycle while this approach requires

two comparison cycles, hence 2-step flash.

This architecture is further simplified in the LTC1099 by

reusing the MS-Flash hardware to do the LS-Flash. This

reduces the number of comparators from 31 to 16. This is

possible because the MS and LS conversions are done at

different times.

To take the simple block diagram of Figure 5 and reconfigure

it to reuse the MS-Flash to do the LS-Flash is conceptually

simple, but from a hardware point of view is not practical.

A new six input switched capacitor comparator is used to

∑

–

4-BIT

FLASH

4-BIT

FLASH

4-BIT

DAC

VREF/16

VIN

VREF

1099 F05

REMAINDER

accomplish this function in a simple, although not straight

forward, manner.

Figure 6 shows the six input switched capacitor compara-

tor. Intuitively, the comparator is easy to understand by

noting that the common connection between the two input

capacitors, C1 and C2, acts like a virtual ground. In

operational amplifier circuits, current is summed at the

virtual ground node. Input voltage is converted to current

by the input resistors. In the switched capacitor compara-

tor, input voltage is converted to charge by the input

capacitors and these charges are summed at the virtual

ground node.

A major advantage of this technique is that the switch-on

impedance has no affect on accuracy as long as sufficient

time exists to fully charge and discharge the capacitors.

During the first time period the T+ and TZ switches are

closed. This forces the common node between C1 and C2

to an arbitrary bias voltage. Since the capacitors subtract

out this voltage, it may be considered, for the sake of this

discussion, to be exactly zero (i.e., virtual ground). Note

Figure 5. 8-Bit 2-Step Semiflash A/D

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